The present invention relates to fuse structures in semiconductor devices. More particularly, the present invention relates to self-aligned fuse structures having anti-reflective coatings, methods of making such fuses, and semiconductor devices incorporating such fuses.
As semiconductor devices, such as integrated circuit chips, continue to decrease in size and increase in complexity, the likelihood of a defective chip resulting from a failed element or a defective conductor increases. One way to reduce the number of chips which must be scrapped due to fabrication defects is to manufacture fuses into semiconductor devices. Fuses may be opened to isolate defective areas and allow the rest of the circuit on a chip to be used. Fuses may also be used to trim a circuit, enable a particular mode, or enable or disable different segments of a circuit.
One example of the use of fuses in semiconductor devices is the provision of redundant elements on integrated circuits. If a primary element is defective a redundant element can be substituted for that defective element, rather than scrapping the chip. An example of a semiconductor device which uses redundant elements is electronic memory. Typical memory chips are composed of millions of equivalent memory cells arranged in addressable rows and columns. Semiconductor memory chips are typically fabricated with built-in redundancy in case one or more bits are found to be bad after fabrication. If a bad bit is found in testing following fabrication, fuses may be blown to "program" a redundant cell to respond to the address of the defective primary cell. The use of the redundant rows and columns in memory cells increases economic efficiency by substantially raising yields. That is, an entire chip need not be rejected in the event that only one or two bits of memory are bad since those bad bits may be replaced by the redundancy built into the chip.
Conventional DRAM and SRAM stand-alone memory cell arrays are typically composed of intersecting rows and columns of polysilicon, metal or silicides. A schematic layout of a typical 64K DRAM array 100, illustrating primary rows 102 and columns 104 of polysilicon, is shown in FIG. 1. These primary rows and columns 102 and 104 are supplemented by redundant rows 106 and columns 108. Rows and columns are typically selected by using row and column decoders 110 and 112, respectively. In the event of the failure of a particular row(s) or column(s), a fuse may be blown to disable the bad bits and enable redundant bits, as described above. Various configurations for incorporating fuses into semiconductor devices to implement redundant elements, such as in electronic memory, and for other applications are well known in the art. Examples are described in U.S. Pat. No. 5,636,172 to Prall et al., and R. T. Smith et al., Laser Programmable Redundancy and Yield Improvement in a 64K DRAM, IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5 (1981), the disclosures of which are incorporated by reference herein for all purposes.
Conventional semiconductor fuses may also be composed of metals or metal alloys, for example, aluminum-copper (AlCu). A typical process for blowing conventional polysilicon fuses involves the use of lasers in conjunction with a fuse structure to program the faulty element(s) out of operation and the redundant element(s) into operation. The conventional approach in using a laser to blow such fuses is to simply irradiate the fuse with a laser beam whose energy density and pulse duration are sufficient to vaporize the fuse material, thereby severing the electrical link.
A recent area in semiconductor device development is embedded memory, which is a combination of memory and logic on the same chip formed during the same fabrication process. For example, an embedded memory cell may include a single silicon layer processed to form transistor devices for both logic and memory functions covered by a series of metal layers which provide routing and interconnects to the silicon layer. Embedded memory cell arrays typically have, for example, two to six metal layers. Since the silicon logic and memory layer is overlaid by metal layers in an embedded memory cell device, it is preferred to use fuses in an upper metal layer to disable bad bits or enable redundant bits built into an embedded memory array. Redundancy is built into embedded memory arrays for the same reason as stand-alone memory, that is, to increase economic efficiency by increasing yield. The conventional process for blowing polysilicon fuses may also be applied to metal fuses. However, since metal does not absorb laser energy as efficiently as polysilicon, the process risks increasing the thermal budget for the overall fabrication process of the device, which may impair its electrical performance.
FIG. 2 is a composite figure showing a conventional semiconductor fuse technology. A cross-sectional side view of the structure of an intact conventional fuse 202 is shown at the center of the figure. A fuse material layer 204, a conductive material, typically composed of polysilicon or a metal or metal alloy, for example aluminum (Al) or aluminum-copper (AlCu), is covered by a blanket of dielectric capping material 206, typically composed of silicon dioxide (SiO.sub.2), of substantially uniform thickness. A typical metal fuse material is about 0.5 to 1.5 .mu.m in width and about 3000 to 5000 .ANG. thick. For a metal fuse width of 1 .mu.m, a recommended pitch is about 2.25 .mu.m with a minimum length of 3.5 .mu.m for a laser with a 2.5 .mu.m beam diameter. As noted above, such a fuse is blown by a laser when the laser's beam incident on the fuse 202 has sufficient energy density and pulse duration to vaporize a portion of the fuse material 204 and sever the electrical connection of which the fuse is part ("blow the fuse").
The wave form 210 at the top of FIG. 2 illustrates the energy distribution of a laser used to blow the fuse 202. A typical laser system used for this purpose is the Model 9300 High-Performance System available from Electro Scientific Industries (ESI). This laser is a diode pumped YLF with a wavelength of 1.047 .mu.m or 1.3 .mu.m, a pulse duration of 4-100 ns, and a maximum energy per pulse of 6 .mu.J. It has an adjustable beam diameter from about 2.5 to 9 .mu.m. Alternatively, a Q-switched Nd-doped YAG laser with about a 4 .mu.J/pulse energy may be used.
A top view of the structure of a blown conventional fuse 202 is shown at the bottom of the figure. The laser energy distribution is represented by the larger of the two concentric circles 212. The smaller circle 214 represents the portion of the incident laser energy having sufficient energy density and pulse duration to blow the fuse.
In designing a laser-blown fuse process, one needs to consider several important topics. First, the width of the fuse, and therefore fuse-to-fuse spacing (i.e., fuse pitch), is limited by the spot (diameter) of the laser beam. Smaller spot sizes allow increased circuit density. As noted above, conventional lasers typically output beams with a minimum diameter of about 2.5 .mu.m. Second, the fuse-blowing process should not affect the operation of the surrounding circuitry. In this respect, fuse materials with lower melting/boiling temperatures, and/or higher absorption coefficients are preferred to minimize thermal exposure. In addition, laser alignment is critical the ensure that the laser beam irradiates the fuse so that it will be blown, and not the surrounding circuitry, to which it could do thermal damage while also possibly not blowing the fuse as desired. Finally, a high-throughput fuse-blowing process is desired. These three demands can be conflicting in designing a fuse-blowing process. For example, although smaller laser-beam sizes reduce fuse pitch, they require more critical alignment, which requires more time and therefore decreases throughput.
Accordingly, semiconductor fuse structures and processes that would allow increased fuse density while reducing thermal exposure and the criticality of laser alignment would be desirable.